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cy62158e mobl ? 8-mbit (1 m 8) static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-05684 rev. *h revised june 10, 2011 8-mbit (1 m 8) static ram features very high speed: 45 ns ? wide voltage range: 4.5 v?5.5 v ultra low active power ? typical active current:1.8 ma at f = 1 mhz ? typical active current: 18 ma at f = f max ultra low standby power ? typical standby current: 2 ? a ? maximum standby current: 8 ? a easy memory expansion with ce 1 , ce 2 and oe features automatic power down when deselected cmos for optimum speed and power offered in pb-free 44-pin tsop ii package functional description the cy62158e mobl ? is a high performance cmos static ram organized as 1024k words by 8 bits. this device features advanced circuit design to provide ultra low active current. this is ideal for providing more battery life? (mobl ? ) in portable applications such as cellular telephones. the device also has an automatic power down feature that significantly reduces power consumption. placing the device into standby mode reduces power consumption significantly when deselected (ce 1 high or ce 2 low). to write to the device, take chip enables (ce 1 low and ce 2 high) and write enable (we ) input low. data on the eight i/o pins (i/o 0 through i/o 7 ) is then written into the location specified on the address pins (a 0 through a 19 ). to read from the device, take chip enables (ce 1 low and ce 2 high) and oe low while forcing the we high. under these conditions, the contents of the memory location specified by the address pins appear on the i/o pins. the eight input and output pins (i/o 0 through i/o 7 ) are placed in a high impedance state when the device is deselected (ce 1 high or ce 2 low), the outputs are disabled (oe high), or a write operation is in progress (ce 1 low and ce 2 high and we low). see the truth table on page 11 for a complete description of read and write modes. logic block diagram a 0 io 0 io 7 io 1 io 2 io 3 io 4 io 5 io 6 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 sense amps power down we oe a 13 a 14 a 15 a 16 row decoder column decoder 1024k x 8 array data in drivers a 10 a 11 a 17 ce 1 ce 2 a 12 a 18 a 19 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 [+] feedback
cy62158e mobl ? document #: 38-05684 rev. *h page 2 of 16 contents pin configuration ............................................................. 3 product portfolio .............................................................. 3 maximum ratings ............................................................. 4 operating range ............................................................... 4 electrical characteristics ................................................. 4 capacitance ...................................................................... 5 thermal resistance .......................................................... 5 ac test loads and waveforms ....................................... 5 data retention characteristics ....................................... 6 data retention waveform ................................................ 6 switching characteristics ................................................ 7 switching waveforms ...................................................... 8 truth table ...................................................................... 11 ordering information ...................................................... 12 ordering code definitions ..... .................................... 12 package diagrams .......................................................... 13 acronyms ........................................................................ 14 document conventions ................................................. 14 units of measure ....................................................... 14 document history page ................................................. 15 sales, solutions, and legal information ...................... 16 worldwide sales and design s upport ......... .............. 16 products .................................................................... 16 psoc solutions ......................................................... 16 [+] feedback
cy62158e mobl ? document #: 38-05684 rev. *h page 3 of 16 pin configuration figure 1. 44-pin tsop ii (top view) [1] 1 2 3 4 5 6 7 8 9 11 14 31 32 36 35 34 33 37 40 39 38 12 13 41 44 43 42 16 15 29 30 a 5 18 17 20 19 23 28 25 24 22 21 27 26 a 6 a 7 a 4 a 3 a 2 a 1 a 0 a 17 a 18 a 10 a 11 a 12 a 13 a 15 a 16 a 14 oe ce 2 a 8 ce 1 we nc nc i/o 0 i/o 1 i/o 2 i/o 3 nc nc nc nc i/o 4 i/o 5 i/o 6 i/o 7 nc nc v cc v cc v ss v ss a 9 10 a 19 product portfolio product v cc range (v) speed (ns) power dissipation operating i cc (ma) standby i sb2 ( ? a) f = 1 mhz f = f max min typ [2] max typ [2] max typ [2] max typ [2] max cy62158ell 4.5 5.0 5.5 45 1.8 3 18 25 2 8 notes 1. nc pins are not connected on the die. 2. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25 c. [+] feedback
cy62158e mobl ? document #: 38-05684 rev. *h page 4 of 16 maximum ratings exceeding maximum ratings may shorten the useful life of the device. user guidelines are not tested. storage temperature ................ ............... ?65 c to +150 c ambient temperature with power applied ........... ............... ............... ?55 c to +125 c supply voltage to ground potential .......................... ?0.5 v to v cc(max) + 0.5 v dc voltage applied to outputs in high z state [3, 4] ......................?0.5 v to v cc(max) + 0.5 v dc input voltage [3, 4] ..................?0.5 v to v cc(max) + 0.5 v output current into outputs (low) ............................ 20 ma static discharge voltage ......................................... > 2001 v (mil-std-883, method 3015) latch up current .................................................... > 200 ma operating range device range ambient temperature v cc [5] cy62158ell industrial ?40 c to +85 c 4.5 v?5.5 v electrical characteristics over the operating range parameter description test conditions -45 unit min typ [6] max v oh output high voltage i oh = ?1 ma 2.4 ? ? v v ol output low voltage i ol = 2.1 ma ? ? 0.4 v v ih input high voltage v cc = 4.5 v to 5.5 v 2.2 ? v cc + 0.5 v v v iil input low voltage v cc = 4.5 v to 5.5 v ?0.5 ? 0.8 v i ix input leakage current gnd < v i < v cc ?1 ? +1 ? a i oz output leakage current gnd < v o < v cc , output disabled ?1 ? +1 ? a i cc v cc operating supply current f = f max = 1/t rc v cc = v cc(max) i out = 0 ma cmos levels ?1825ma f = 1 mhz 1.8 3 ma i sb1 automatic ce power down current ? cmos inputs ce 1 > v cc ?? 0.2 v, ce 2 < 0.2 v v in > v cc ? 0.2 v, v in < 0.2 v f = f max (address and data only), f = 0 (oe , and we ), v cc = v ccmax ?28 ? a i sb2 [7] automatic ce power-down current ? cmos inputs ce 1 > v cc ? 0.2 v or ce 2 < 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v, f = 0, v cc = v ccmax ?28 ? a notes 3. v il (min) = ?2.0 v for pulse durations less than 20 ns. 4. v ih (max) = v cc + 0.75 v for pulse durations less than 20 ns. 5. full device ac operation assumes a 100 ? s ramp time from 0 to v cc (min) and 200 ? s wait time after v cc stabilization. 6. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25 c. 7. chip enables (ce 1 and ce 2 ), must be tied to cmos levels to meet the i sb1 / i sb2 / i ccdr spec. other inputs can be left floating. [+] feedback
cy62158e mobl ? document #: 38-05684 rev. *h page 5 of 16 capacitance parameter [8] description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = v cc(typ) 10 pf c out output capacitance 10 pf thermal resistance parameter [8] description test conditions 44-pin tsop ii unit ? ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, two-layer printed circuit board 75.13 ? c/w ? jc thermal resistance (junction to case) 8.95 ? c/w ac test loads and waveforms figure 2. ac test loads and waveforms 3 v v cc output r2 100 pf including jig and scope gnd 90% 10% 90% 10% rise time = 1 v/ns fall time = 1 v/ns output v equivalent to: thvenin equivalent all input pulses r th r1 parameters 5.0 v unit r1 1838 ? r2 994 ? r th 645 ? v th 1.75 v note 8. tested initially and after any design or process changes that may affect these parameters. [+] feedback
cy62158e mobl ? document #: 38-05684 rev. *h page 6 of 16 data retention characteristics over the operating range parameter description conditions min typ [9] max unit v dr v cc for data retention 2 ? ? v i ccdr [10] data retention current v cc = v dr ce 1 > v cc ? 0.2 v, ce 2 < 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v ??8 ? a t cdr [11] chip deselect to data retention time 0??ns t r [12] operation recovery time 45 ? ? ns data retention waveform figure 3. data retention waveform v cc (min) v cc (min) t cdr v dr > 2.0 v data retention mode t r ce 1 v cc ce 2 or notes 9. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25 c. 10. chip enables (ce 1 and ce 2 ), must be tied to cmos levels to meet the i sb1 / i sb2 / i ccdr spec. other inputs can be left floating. 11. tested initially and after any design or process changes that may affect these parameters. 12. full device operation requires linear v cc ramp from v dr to v cc (min) > 100 ? s or stable at v cc (min) > 100 ? s. [+] feedback
cy62158e mobl ? document #: 38-05684 rev. *h page 7 of 16 switching characteristics over the operating range parameter [13] description 45 ns unit min max read cycle t rc read cycle time 45 ? ns t aa address to data valid ? 45 ns t oha data hold from address change 10 ? ns t ace ce 1 low and ce 2 high to data valid ? 45 ns t doe oe low to data valid ? 22 ns t lzoe oe low to low z [14] 5 ? ns t hzoe oe high to high z [14, 15] ? 18 ns t lzce ce 1 low and ce 2 high to low z [14] 10 ? ns t hzce ce 1 high or ce 2 low to high z [14, 15] ? 18 ns t pu ce 1 low and ce 2 high to power up 0 ? ns t pd ce 1 high or ce 2 low to power down ? 45 ns write cycle [16] t wc write cycle time 45 ? ns t sce ce 1 low and ce 2 high to write end 35 ? ns t aw address setup to write end 35 ? ns t ha address hold from write end 0 ? ns t sa address setup to write start 0 ? ns t pwe we pulse width 35 ? ns t sd data setup to write end 25 ? ns t hd data hold from write end 0 ? ns t hzwe we low to high z [14, 15] ? 18 ns t lzwe we high to low z [14] 10 ? ns notes 13. test conditions for all parameters other than tri-state paramete rs assume signal transition time of 3 ns or less (1 v/ns), t iming reference levels of v cc(typ) /2, input pulse levels of 0 to v cc(typ) , and output loading of the specified i ol /i oh as shown in figure 2 on page 5 . 14. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 15. t hzoe , t hzce , and t hzwe transitions are measured when the outputs enter a high impedance state. 16. the internal write time of the memory is defined by the overlap of we , ce 1 = v il , and ce 2 = v ih . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input setup and hold timing should be referenced to the edge of the signal th at terminates the write. [+] feedback
cy62158e mobl ? document #: 38-05684 rev. *h page 8 of 16 switching waveforms figure 4. read cycle no. 1 (address transition controlled) [17, 18] figure 5. read cycle no. 2 (oe controlled) [18, 19] address data out previous data valid data valid t rc t aa t oha 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzce t pd high i cc i sb impedance oe ce 1 address ce 2 data out supply current v cc notes 17. device is continuously selected. oe , ce 1 = v il , ce 2 = v ih . 18. we is high for read cycle. 19. address valid before or similar to ce 1 transition low and ce 2 transition high. [+] feedback
cy62158e mobl ? document #: 38-05684 rev. *h page 9 of 16 figure 6. write cycle no. 1 (we controlled) [20, 21, 22] figure 7. write cycle no. 2 (ce 1 or ce 2 controlled) [20, 21, 22] switching waveforms (continued) t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe valid data note 23 ce 1 address ce 2 we data i/o oe t wc valid data t aw t sa t pwe t ha t hd t sd t sce ce 1 address ce 2 we data i/o oe notes 20. the internal write time of the memory is defined by the overlap of we , ce 1 = v il , and ce 2 = v ih . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input setup and hold timing should be referenced to the edge of the signal th at terminates the write. 21. data i/o is high impedance if oe = v ih . 22. if ce 1 goes high or ce 2 goes low simultaneously with we high, the output remains in high impedance state. 23. during this period, the i/os are in output state. do not apply input signals. [+] feedback
cy62158e mobl ? document #: 38-05684 rev. *h page 10 of 16 figure 8. write cycle no. 3 (we controlled, oe low) [24] switching waveforms (continued) valid data t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe note 25 ce 1 address ce 2 we data i/o notes 24. if ce 1 goes high or ce 2 goes low simultaneously with we high, the output remains in high impedance state. 25. during this period, the i/os are in output state. do not apply input signals. [+] feedback
cy62158e mobl ? document #: 38-05684 rev. *h page 11 of 16 truth table ce 1 ce 2 we oe inputs/outputs mode power h x [26] x x high z deselect/power down standby (i sb ) x [26] l x x high z deselect/power down standby (i sb ) l h h l data out read active (i cc ) l h h h high z output disabled active (i cc ) l h l x data in write active (i cc ) note 26. the ?x? (don?t care) state for the chip enables in the truth table refer to the logic state (either high or low). intermedia te voltage levels on these pins is not permitted. [+] feedback
cy62158e mobl ? document #: 38-05684 rev. *h page 12 of 16 ordering information speed (ns) ordering code package diagram package type operating range 45 CY62158ELL-45ZSXI 51-85087 44-pin tsop ii (pb-free) industrial contact your local cypress sales repres entative for availability of this part. ordering code definitions temperature grade: i = industrial pb-free package type: zs = 44-pin tsop ii speed grade: 45 ns ll = low power process technology: 90 nm bus width = 8 density = 8-mbit family code: mobl sram family company id: cy = cypress cy -zs 621 5 8 e ll i 45 x [+] feedback
cy62158e mobl ? document #: 38-05684 rev. *h page 13 of 16 package diagrams figure 9. 44-pin tsop z44-ii, 51-85087 max min. dimension in mm (inch) (optional) can be located anywhere in the bottom pkg ejector mark z a z z z z x a 10.058 (0.396) 10.262 (0.404) 0.597 (0.0235) 0.406 (0.0160) 0.210 (0.0083) 0.120 (0.0047) top view bottom view plane seating 18.517 (0.729) 0.800 bsc 0-5 0.400(0.016) 0.300 (0.012) 1.194 (0.047) 0.991 (0.039) 0.150 (0.0059) 0.050 (0.0020) (0.0315) 18.313 (0.721) base plane 0.10 (.004) 11.938 (0.470) pin 1 i.d. 44 1 11.735 (0.462) 10.058 (0.396) 10.262 (0.404) 22 23 51-85087 *c [+] feedback
cy62158e mobl ? document #: 38-05684 rev. *h page 14 of 16 acronyms document conventions units of measure acronym description ce chip enable cmos complementary metal oxide semiconductor i/o input/output oe output enable sram static random access memory tsop thin small outline package we write enable symbol unit of measure c degree celsius mhz mega hertz ? a micro amperes ? s micro seconds ma milli amperes ns nano seconds ? ohms % percent pf pico farad v volts w watts [+] feedback
cy62158e mobl ? document #: 38-05684 rev. *h page 15 of 16 document history page document title: cy62158e mobl ? , 8-mbit (1 m 8) static ram document number: 38-05684 rev. ecn no. issue date orig. of change description of change ** 270350 see ecn pci new data sheet *a 291271 see ecn syt converted from ad vance information to preliminary changed input pulse level from v cc to 3v in the ac test loads and waveforms modified footnote #9 to include timing reference level of 1.5v and input pulse level of 3v *b 1462592 see ecn vkn/aesa convert ed from preliminary to final removed 35 ns speed bin removed ?l? parts removed 48-ball vfbga package changed i cc(max) spec from 2.3 ma to 3 ma at f=1 mhz changed i cc(typ) spec from 16 ma to 18 ma at f=f max changed i cc(max) spec from 28 ma to 25 ma at f=f max changed i sb1(typ) and i sb2(typ) spec from 0.9 ? a to 2 ? a changed i sb1(max) and i sb2(max) spec from 4.5 ? a to 8 ? a changed i ccdr(max) spec from 4.5 ? a to 8 ? a changed t lzoe spec from 3 ns to 5 ns changed t lzce spec from 6 ns to 10 ns changed t hzce spec from 22 ns to 18 ns changed t pwe spec from 30 ns to 35 ns changed t sd spec from 22 ns to 25 ns changed t lzwe spec from 6 ns to 10 ns added footnote# 6 related to i sb2 and i ccdr updated ordering information table *c 2428708 see ecn vkn/pyrs corrected typo in the ordering information table *d 2516494 see ecn pyrs corrected ecn number *e 2934396 06/03/10 vkn added footnote #19 related to chip enable updated package diagram updated template *f 3110202 12/14/2010 pras updated logic block diagram. added ordering code definitions. *g 3121955 12/28/2010 srih updated the missi ng header and footer in pg 12. *h 3279426 06/10/2011 rame updated functional description (removed ?for best practice recommendations, refer to the cypress application note an1064, sram system guidelines?). updated data retention characteristics . added acronyms and units of measure . updated in new template. [+] feedback
document #: 38-05684 rev. *h revised june 10, 2011 page 16 of 16 all products and company names mentioned in this document may be the trademarks of their respective holders. cy62158e mobl ? ? cypress semiconductor corporation, 2004-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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